1. Field of the Invention
The present invention relates to a circuit simulation method, and more particularly, to a circuit simulation method for a circuit having a well resistor.
2. Description of Related Art
Along with miniaturization of semiconductor integrated circuits, an area of logic circuits is reduced, whereas, an area of analog circuits is not necessarily reduced. Therefore, reduction of the area of analog circuits has become an increasingly critical issue for cost reduction. A cause of an impediment to reducing the area of analog circuits is that it is difficult to reduce the area of resistors. Here, a terminal region (an opening) of a well resistor is connected to a wiring line through a tap and a plurality of contacts which are regularly arranged on the tap. It is difficult to estimate the value of a resistance of the terminal region of the resistor (hereinafter referred to as “terminal parasitic-resistance”) precisely.
When there is an estimation error of the terminal parasitic-resistance, it is necessary to enlarge a margin for the estimation error or to design the layout in which the estimation error is negligible. In each case, the circuit area increases. In particular, a resistance of contacts which are one of major components of the terminal parasitic-resistance increases at an accelerated rate along with the recent miniaturization. Therefore, the terminal parasitic-resistance becomes large relative to a resistance of the main body of the resistor. Thus, the estimation error of the terminal parasitic-resistance has become an increasingly significant issue.
In general, to estimate the terminal parasitic-resistance, it is necessary to extract a complex parasitic-resistance net by using an LPE (Layout Parameter Extraction) tool after layout design. Further, to shorten a circuit simulation time, a circuit reduction needs to be performed by a sequential hand calculation or a circuit reduction tool. However, such methods require time and effort or include estimation errors due to an LPE tool.
When reviewing the circuit design after estimation using an LPE tool, the design efficiency is significantly lowered. Thus, in the circuit design stage before the layout design, the terminal parasitic-resistance is required to be estimated. In this case, since the LPE tool cannot be used, the terminal parasitic-resistance has simply been estimated up to now. Specifically, the terminal parasitic-resistance is considered to be inversely proportional to the area of the opening. As a similar attitude, in Japanese Unexamined Patent Application Publication No. 7-49897, the parasitic-resistance of the emitter of a bipolar transistor is modeled by being considered to be inversely proportional to the area of the opening of a diffusion layer.